The present invention relates to semiconductor devices, such as, for example, static random access memories (SRAMs), and memory systems and electronic apparatuses provided with the same.
SRAMS, one type of semiconductor memory devices, do not require a refreshing operation and therefore have a property that can simplify the system and lower power consumption. For this reason, the SRAMs are prevailingly used as memories for electronic equipment, such as, for example, mobile phones.
The present invention provides a semiconductor device that can reduce its cell area.
The present invention also provides a memory system and an electronic apparatus that includes a semiconductor device in accordance with the present invention.
1. Semiconductor Device
According to one aspect of the present invention, there is provided a semiconductor device including a first conduction type well region and a second conduction type well region.
The semiconductor device also includes a first gate-gate electrode layer including a gate electrode of a first load transistor and a gate electrode of the first driver transistor and a second gate-gate electrode layer including a gate electrode of a second load transistor and a gate electrode of the second driver transistor. The semiconductor device further includes a first drain-drain wiring layer that forms a part of a connection layer that electrically connects a drain region of the first load transistor and a drain region of a first driver transistor and a second drain-drain wiring layer that forms a part of a connection layer that electrically connects a drain region of the second load transistor and a drain region of a second driver transistor. The semiconductor device also includes a first drain-gate wiring layer that forms a part of a connection layer that electrically connects the first gate-gate electrode layer and the second drain-drain wiring layer and a second drain-gate wiring layer that forms a part of a connection layer that electrically connects the second gate-gate electrode layer and the first drain-drain wiring layer.
The first load transistor and the second load transistor are provided in the first conduction type well region and first driver transistor and the second driver transistor are provided in the second conduction type well region. The second drain-gate wiring layer is located in a layer over the first drain-gate wiring layer, and has an upper layer of the second drain-gate wiring layer and a lower layer of the second drain-gate wiring layer. The upper layer is located in a layer over the lower layer and the upper layer is provided above one of the first conduction type well region and the second conduction type well region.